PCILMR(8) The PCI Utilities PCILMR(8) (NAME) pcilmr - PCIe (Lane Margin Tool) (SYNOPSIS) pcilmr [--margin] [] [] [ [] ...] pcilmr --full [] pcilmr --scan (CONFIGURATION) (margining). BIOS ( Xeon ): o PCIe Leaky Bucket (Re-Equalization) (Link Degradation) o (Error Thresholds) 0 o Intel VMD NVMe SSD - pcilmr VMD . (): : o 16.0 GT/s ( 16 GT/s 32 GT/s ) o (Downstream Component) D0 . : o ASPM (Downstream Port) (Upstream Port) o Hardware Autonomous Speed Disable Link Control 2 (Set) o Hardware Autonomous Width Disable Link Control (Set) . (DESCRIPTION) pcilmr PCIe (PCIe Lane Margining at the Receiver) 16.0 GT/s (Retimers) . Lane Margining at the Receiver L0 . . 16.0 GT/s 32.0 GT/s . . (eye margin diagram) ( ) . Lane Margining at the Receiver PCIe . . pcilmr (root) ( ) . (RESULTS GRADING) PCIe pcilmr . 8.4.2 PCIe Base Spec Rev. 5.0 . PCIe Architecture PHY Test Spec Rev 5.0 (Transmitter Electrical Compliance) . : +----+----------------------+--------------------------+ | | 16 GT/s (Gen 4) | 32 GT/s (Gen 5) | | | EW | EH | EW | EH | +----+--------------+-------+---------------+----------+ |Min | 18.75 ps 30% | 15 mV | 9.375 ps 30% | 15 mV | | | UI | | UI | | +----+--------------+-------+---------------+----------+ |Rec | 23.75 ps 38% | 21 mV | 10.157 ps 33% | 19.75 mV | | | UI | | UI | | +----+--------------+-------+---------------+----------+ pcilmr (EW EH) . . EW EH . -g ( ). (HARDWARE QUIRKS SUPPORT) . - (Vendor ID - Device ID) . margin_hw (hardcoded). . RC Ice Lake pcilmr MaxVoltageOffset 'one side is the whole' . (OPTIONS) (Device Specifier) (Downstream) (Upstream) . [:]:. ( lspci(8)) (Utility Modes) --margin ... . --full ( --scan ) . --scan 16 GT/s . Margining Ready "Ready" () . ( ) -c (Device Lane Margining Capabilities). . -e (Error Count Limit) . : 4. -o csv . "lmr__Rx#_.csv" . -d